New Technology Reduces 30% Chip Area of STT-MRAM While Increasing Memory Bit Yield By 70% (IMAGE)

Tohoku University

New Technology Reduces 30% Chip Area of STT-MRAM While Increasing Memory Bit Yield By 70%

Caption

Fabricated 2-Mbit MRAM test chip for verifying the developed MTJ formation technology directly on via hole in VLSI.

Credit

Yoichi Oshima

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Credit: Yoichi Oshima

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