Figure 1. Photograph of a Chip Containing the Proposed PLL (IMAGE)

_Tokyo Institute of Technology

Figure 1. Photograph of a Chip Containing the Proposed PLL

Caption

The entire all-digital PLL fits in a 50 × 72 μm2 region, making it the smallest PLL to date.

Credit

Kenichi Okada

Usage Restrictions

None

License

Licensed content

Disclaimer: AAAS and EurekAlert! are not responsible for the accuracy of news releases posted to EurekAlert! by contributing institutions or for the use of any information through the EurekAlert system.