LEES Researcher Reviewing a 200 mm Silicon Iii-V Wafer (IMAGE)

Singapore-MIT Alliance for Research and Technology (SMART)

LEES Researcher Reviewing a 200 mm Silicon Iii-V Wafer

Caption

LEES researcher reviewing a 200 mm Silicon III-V wafer. The innovative and commercial-ready process by LEES leverages existing 200 mm semiconductor manufacturing infrastructure to create a new generation of chips that combines traditional Silicon with III-V devices, something not commercially viable before.

Credit

SMART

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