Figure 1. Design of the Layered Three-Valued Memory Cell (IMAGE)

_Tokyo Institute of Technology

Figure 1. Design of the Layered Three-Valued Memory Cell

Caption

The stacked layers in the proposed memory device form a mini-battery that can be quickly and efficiently switched between three different voltage states (0.95 V, 1.35 V, and 1.80 V).

Credit

ACS Applied Materials and Interfaces

Usage Restrictions

None

License

Licensed content

Disclaimer: AAAS and EurekAlert! are not responsible for the accuracy of news releases posted to EurekAlert! by contributing institutions or for the use of any information through the EurekAlert system.