As electronic circuits become more compact, the individual, overlapping wires are crammed so close together that their signals interfere with each other, causing devices to work more slowly or to fail.
Now, a Purdue University researcher is proposing a novel design strategy to reduce the interference. His method also might enable engineers to predict how the tiny circuits will perform long before building the first prototype, which would speed development and reduce costs.
Unlike conventional circuit designs, the new method takes into account two factors that lie at the heart of the interference. First, the thin metal lines that conduct electricity often overlap. Second, in two parallel lines that are close to each other, the electrical current often travels in the opposite directions. Both factors increase the degree of "interwire capacitance," or the unwanted storage of electricity in the insulating material between the wires.
That stored electricity builds up until it eventually discharges, hindering the circuit's overall performance, slowing down a device's operating speed, and, in some cases, causing the circuit to fail, says Kaushik Roy, an associate professor in Purdue's School of Electrical and Computer Engineering. Details about his design method will be discussed during an engineering conference in May.
The capacitance problem will become more severe in a new generation of circuits designed to operate at lower power than conventional devices. By consuming less electricity, the devices will use lighter-weight batteries and run longer on a single charge. However, the interference between wires causes those types of low-power circuits to malfunction more frequently than conventional circuits.
In Roy's method, the capacitance is decreased significantly by designing circuits so that the electrical current in parallel wires is transmitted in the same direction. "This is a layout that is based on the direction of current," Roy says. "Most architectures don't do that." The wires also are arranged to reduce the degree with which they overlap.
Doctoral student Yonghee Im will present a research paper about the work May 24, during the Custom Integrated Circuits Conference, sponsored by the Institute of Electrical and Electronics Engineers, in Orlando, Fla.
The approach might be used for the "predictable design" of future circuits containing features billionths of a meter in diameter, or, in the "nanometer" range, he says. In such compact circuits, wires and transistors -- the solid-state switches without which modern electronics would be impossible -- are crammed closer together than they would be in more conventional designs. Engineers would ideally like to know how interwire capacitance would affect the performance of new designs before actually building the circuits.
"Then they would know whether to even pursue a specific architecture," says Roy, who has developed a computer model for predicting a design's performance ahead of time.
Writer: Emil Venere, 765-494-4709, evenere@uns.purdue.edu
Related Web sites: Kaushik Roy's Web page: http://min.ecn.purdue.edu/~kaushik/ Web site for the Custom Integrated Circuits Conference: http://www.his.com/~cicc/ Web site for the Institute of Electrical and Electronics Engineers: http://www.ieee.org/
ABSTRACT A Novel High-Performance Predictable Circuit Architecture for the Deep Sub-micron Era Yonghee Im and Kaushik Roy
Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. Those goals have been accomplished mainly by deep sub-micron technology along with voltage scaling. However, scaling down feature size causes larger cross talk between concerned interconnects. We are currently facing signal integrity problems never experienced before, such that accurate function predictability of circuits under certain input conditions may be questionable, not to mention performance and power dissipation predictability. In this paper we suggest a novel predictable circuit architecture, named optimized overlaying array based architecture (O2 ABA), especially suited for the deep sub-micron regime. O2 ABA achieves reduction of cross talk by considering the current directions and by reducing interwire capacitance. The introduction of unit cell leads to high regularity, which makes the performance predictable even before layout, and shortens time-to-design. O2 ABA is compared with other design styles, such as custom design, PLA and Weinberger array, to show its advantages.
NOTE TO JOURNALISTS: A copy of the research paper referred to in this news release is available from Emil Venere at the Purdue News Service, 765-494-4709, evenere@uns.purdue.edu