Public Release: 

UCSD engineers win student chip-design prize

Chip reduces power consumption of 3g cell phone transmitter

University of California - San Diego

San Diego, CA, September 5, 2003 -- A team from the University of California, San Diego (UCSD) Jacobs School of Engineering is one of three winners in the premier international student chip-design competition organized by the Semiconductor Research Corporation® (SRC). The UCSD team took second place for its development of novel techniques to dramatically improve talk times in third-generation (3G) cell phones by reducing average power consumption by about 50%.

Nearly 60 university teams from around the world competed in the SRC Silicon Germanium (SiGe) Design Challenge, which began in May 2002. Jacobs School electrical and computer engineering (ECE) graduate student Vincent Leung was advised on the project by ECE professor Lawrence Larson and visiting lecturer Prasad Gudem. The research was underwritten by UCSD's Center for Wireless Communications (CWC) and a state-funded UC Discovery Grant awarded in 2001. "This is probably the most intense effort by a graduate student I have ever witnessed," said Larson, who also directs the CWC. "Vincent's design was more complicated than the others, and he did 99% of the work himself."

Leung designed an "Ultra-Low-Power SiGe BiCMOS Transmitter IC for 3G W-CDMA Mobile Phone Applications." A 3G cell phone can cut back its signal amplitude, depending on how far it is from the base station. But even putting out a weaker signal, the handset draws roughly the same amount of power from the battery. "Through a combination of architecture and circuit innovations, we developed a technique to lower power consumption considerably, especially when the handset is very close to the base station," said Leung. "In a nutshell, that's the basic innovation: 'current on demand,' thanks to a smart, adaptive bias, scheme."

The third-year grad student had six months to design the chip from scratch, and his design was picked to be one of 15 entries fabricated in IBM 0.25 micron BiCMOS SiGe 6HP technology through MOSIS fabrication services. The circuits came back from IBM's foundry in June, and teams had five weeks to do final testing. "Vincent's chip was very highly integrated, but it came back working the very first time," observed Larson. "That took a lot of work and a lot of simulation beforehand, and it's a testament to his thoroughness, care, and brilliant engineering."

SiGe technology has recently become key to the development of high performance digital, mixed-signal and wireless integrated circuit products. "This technology is very sophisticated in a lot of areas," said Leung. "It handles digital capabilities really well, analog and RF capabilities, isolation, and so on. Our architecture makes use of those aspects, including very high-speed digital logic, high-speed switching with very low current consumption, as well as high-quality inductors integrated on the chip."

As for the future of the technology, Larson says to implement it would require a slight change of interface, which is not yet a standard feature of today's 3G cell phones. But "we expect to file patents on one or two of the key techniques in this research," said the CWC director, "and our member companies could use this intellectual property in designing future cell phones."

The top three winning teams were from, respectively, the University of Minnesota, UCSD, and Cornell University. Leung's project won a $15,000 cash prize, to be used by the CWC for future chip fabrication and other services. Leung and Larson accepted their award in Dallas on August 29 at SRC's annual student conference, TECHCON 2003. Co-sponsors of the Design Challenge included IBM, National Semiconductor, Cadence Design Systems, Artisan, and MOSIS.


SRC is a global industrial consortium that plans and manages the largest, continuous, industry-driven basic and applied university research program in semiconductor technology. Said Dinesh Mehta, SRC vice president and general chair of TECHCON 2003: "SRC design contests have been one of the most productive tools for bringing together new technologies, students and industry." Since 1982, SRC has invested more than a half-billion dollars in university research on behalf of its member companies. SRC is based in Research Triangle Park, N.C., with an office in San Jose, Calif.

(Photo of Larson, Leung and the winning chip design available on request.)

Media Contact: Doug Ramsey 858-822-5825

Related Links:

UCSD Center for Wireless Communications
Semiconductor Research Corp.
UC Discovery Grants
National Semiconductor
Cadence Design Systems

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