Intel Corp. and the National Science Foundation (NSF) have turned to Michael Hsiao, associate professor of electrical and computer engineering at Virginia Tech, to help meet these challenges.
Hsiao is creating tools that will save time and improve accuracy in the design, testing and verification of computer chips. The tools will be useful throughout the semiconductor industry and could help keep down the future costs of chips -- and computers.
Working with a $225,000 grant from NSF, Hsiao is developing graph-theoretic algorithms (problem-solving mathematical procedures) to reduce the time it takes to verify chips against errors. "Semiconductor chips are becoming far more complex and about 70 percent of design time is dominated by verification," Hsiao said. "We have already achieved an order-of-magnitude breakthrough toward our goal of reducing verification costs, and hope to have another breakthrough soon." Hsiao's approach in the NSF-sponsored project involves using non-conventional methods to perform accelerated state-space exploration, a key step in design verification.
Intel has awarded Hsiao a $120,000 grant to work on testing high-performance chips.
Each Pentium chip is tested before it is shipped, Hsiao explained. Before the technology reached today's high speeds, testing was not a significant problem. Higher "clock rates," the speed at which computer chips process instructions, along with other design advances make chips more vulnerable to speed-related failures.
During the past 30 years, Intel has increased the clock rate of its computer chips from several MHz (megahertz -- or million cycles per second) to a top speed today of 3 GHz (gigahertz -- or billion cycles per second). Intel's Pentium 4 chip, for example, is designed to operate between 2 to 3 GHz
"It's already a daunting task to test a 3 GHz chip. It is critical to ensure that each chip works at the correct processor speed and that it won't fail at the rated clock," Hsiao said. "But testing will become even more of a problem as Intel moves on to the next generation processor, which will operate at speeds greater than 3 GHz."
Hsiao's goal is to develop state-of-the-art algorithms and tools that will significantly decrease the time required to test the performance of each chip manufactured.
Hsiao, who joined the Virginia Tech faculty in 2001, has a successful record in this area of research. In 2000, while he was teaching at Rutgers University, he won a highly competitive NSF Faculty Early Career Development Program (CAREER) grant for his work on functional testing of semiconductor chips.
Reach Dr. Hsiao at 540-231-9254 or email@example.com
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