The model is the first method that can be used to simultaneously evaluate the reliability of two types of transistors essential for so-called CMOS computer chips, the most common type of integrated circuits in use today. The two types of transistors degrade differently over time, and the model is able to relate these two different classes of degradation simultaneously.
"It is the first single tool for accurately predicting how new designs for both types of transistors will degrade over time," said Ashraf Alam, a professor of electrical and computer engineering at Purdue.
The degradation revolves around bonds between atoms of hydrogen and silicon and hydrogen and silicon dioxide. Specifically, the mathematical model enables researchers to see the rates at which these hydrogen bonds in the two types of transistors will break over time. The breaking bonds are directly related to a transistor's long-term reliability. Because hydrogen bonds break differently in the two types of transistors, separate models have been required in conventional testing for new designs.
"This testing requires a huge amount of resources, costing companies millions of dollars annually," Alam said. "If you could explain both within the same framework, then you could cut down significantly on the number of measurements required to characterize the performance of the transistors."
Findings about the new model will be detailed in a research paper to be presented Dec. 13 during the 50th annual IEEE International Electron Devices Meeting, sponsored by the Institute of Electrical and Electronics Engineers, in San Francisco. The paper was written by Alam and Purdue engineering doctoral student Haldun Kufluoglu.
"A major goal of reliability models is to predict how well electronic components will work perhaps 10 years after they are manufactured," Alam said. "In order to do that, you first need to be able to understand the devices very well so that you can extrapolate how reliable they will be in the future.
"You need to understand the details of how the device operates and how various materials behave over time so that you can see how the different chemical bonds will gradually break and how the integrated circuit will gradually lose its function. For a multibillion dollar electronics industry, that knowledge has huge implications."
Bonds between silicon and hydrogen are critical to the proper performance of transistors.
"Even for the tiniest transistor today, there are perhaps thousands of these silicon-hydrogen bonds," Kufluoglu said. "These bonds gradually break. Initially, it doesn't matter because there are so many of these bonds. But over a period of time, when lots of them begin to break, the different transistors within an integrated circuit start getting out of synch."
CMOS, or complementary metal oxide semiconductor chips, are made of PMOS and NMOS transistors, both of which are essential for CMOS integrated circuits. Integrated circuits inside computers contain equal parts of PMOS (positive polarity) and NMOS (negative polarity) transistors.
"The important point is that the mechanisms by which the silicon-hydrogen bonds break are different for these two types of transistors," Alam said. "And that is why, for the past 30 years, we have treated these processes with separate models, because we didn't know how to put them in a common framework, or a common language, mathematically."
The paper describes the underlying mechanism for the breaking bonds in the two types of transistors, he said.
The model not only describes the rate at which the silicon-hydrogen bonds break, but also how they "repair" themselves.
"If you don't use your computer for some period of time, say 24 hours, gradually the hydrogen that went away will diffuse back and combine with silicon to make the bond whole again," Alam said. "Researchers already knew the rates at which the broken bonds are made whole again, but because these rates are much different in the PMOS and NMOS transistors, there was no model that could explain both simultaneously."
The bonds repair themselves much faster in PMOS transistors than in NMOS transistors, he said.
The new model will likely be particularly useful to test the reliability of designs for silicon-based chips that use nanotechnology to create smaller and more compact transistors than exist in today's integrated circuits, Alam said.
Writer: Emil Venere, 765-494-4709, firstname.lastname@example.org
Sources: Ashraf Alam, 765-494-5988, email@example.com
Haldun Kufluoglu, 765-494-9034, firstname.lastname@example.org
Related Web site:
IEEE International Electron Devices Meeting: http://www.
A Geometrical Unification of the Theories of NBTI and HCI Time-Exponents and its Implications for Ultra-Scaled Planar and Surround-Gate MOSFETs
Haldun Kufluoglu and Muhammad Ashraful Alam
School of Electrical and Computer Engineering, Purdue University
A unification of time-exponents for Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is established under the geometric interpretation of interface trap generation. Resolving the fundamental inconsistencies, a numerical reaction-diffusion (R-D) model that agrees with recent measurements is developed. The implications regarding the degradations of future sub-100 nm planar and surround-gate MOSFETs are presented.