News Release

Four University of Texas profs promoted to IEEE Fellow status

UT-Austin electrical & computer engineering researchers honored

Grant and Award Announcement

University of Texas at Austin, Electrical & Computer Engineering

Professor Gustavo DeVeciana, University of Texas at Austin, Electrical & Computer Engineering

image: Professor Gustavo DeVeciana promoted to IEEE Fellow "for contributions to the design of communication networks." view more 

Credit: Cockrell School of Engineering - University of Texas at Austin

The Department of Electrical & Computer Engineering (UT-ECE) is delighted to announce that the Institute of Electrical and Electronics Engineers (IEEE) has elevated four of our faculty to Fellow status, the highest grade of IEEE membership. The standard for advancement is "unusual distinction in the profession" and "extraordinary records of accomplishments [that have] significant value to society."

Professor Gustavo DeVeciana was promoted "for contributions to the design of communication networks." Dr. de Veciana researches wireline and wireless network protocols and architectures. His work involves the measurement, modeling and analysis of traffic, evolving applications, and service requirements towards supporting better network engineering.

He also researches architectural principles of networks supporting sensing and pervasive computing applications, by embedding sensors, storage and computation in the environment. The objective of this work is to enable mobile devices and environments which share contextual information, allowing distributed applications which exhibit location, and more generally context-specific functionality.

Professor Brian L. Evans was elevated to Fellow "for contributions to multicarrier communications and image display." Dr. Evans' research and teaching efforts are in embedded real-time signal and image processing systems. In signal processing, his research group is focused on the design and real-time software implementation of ADSL transceivers and multiuser OFDM systems, with the goal of maximizing connection rates for high-speed Internet access. In transceiver design, his group's primary contribution is the first ADSL equalization structure that maximizes a measure of bit rate and is realizable in real-time fixed-point software. In image processing, his group is focused on the design and real-time software implementation of high-quality halftoning for desktop printers and smart image acquisition for digital still cameras. His group also researches perceptual image hashing and its applications in multimedia authentication, databases, and watermarking. In imaging, his group's primary contribution is in the design, analysis, and quality assessment of halftoning by error diffusion for real-time processing by printer pipelines.

The department's first female IEEE Fellow is Professor Lizy John "for contributions to power modeling and performance evaluation of microprocessors." Dr. John's research centers around designing high-performance microprocessors and computer systems. Her lab specializes in workload characterization and its use for computer system design. Modern workloads are complex because they integrate a variety of software standards and protocols to support the Web portal, shopping cart, credit card transactions, security software layers and more. When microprocessors and computers are in the pre-silicon design stages, they cannot be tested with actual applications with these various layers. Dr. John's team has developed a technique to clone full-blown applications to create miniature versions that can be executed on early design models to accurately estimate performance and power. John's team has also worked on creating power and thermal stress programs (a k a power viruses) to drive designs to extreme conditions and help design robust microprocessors and computer systems.

Another application of the cloning technique from John's group has been to hide the functionality of proprietary applications. Lockheed Martin is supporting John's research to create clones for their proprietary codes, enabling them to share codes without divulging proprietary information.

Professor Nur Touba was named an IEEE Fellow "for contributions to test data compression and built-in self-test for integrated circuits." Dr. Touba has developed a number of innovative techniques for automated design of testable and fault-tolerant circuits. In particular, his research has focused on developing new techniques for built-in self-test (BIST), test data compression, delay fault testing, concurrent error detection, and design-for-testibility (DFT) in core-based designs.

Dr. Touba served as Program Chair for the 2008 International Test Conference, General Chair for the 2007 Symposium on Defect and Fault Tolerance, and Program Chair for 2008 International Test Synthesis Workshop. He is on the program committee for the International Test Conference (ITC), International Conference on Computer Design (ICCD), Design Automation and Test in Europe Conference (DATE), International On-Line Test Symposium (IOLTS), European Test Symposium (ETS), Asian Test Symposium (ATS), Defect and Fault Tolerance Symposium (DFTS), International Test Synthesis Workshop (ITSW), and Latin American Test Workshop (LATW).

These promotions were effective Jan 1, 2009.

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