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Digital PLL achieves a power consumption of 0.265 mW

An ultra-low-power frequency synthesizer targeted for IoT devices

Tokyo Institute of Technology

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IMAGE: This is the proposed fractional-N DPLL occupies an area of 0.25 mm2 in 65-nanometer CMOS. view more 

Credit: Kenichi Okada

Scientists at Tokyo Institute of Technology have developed an advanced phase-locked loop[1] (PLL) frequency synthesizer that can drastically cut power consumption. This digital PLL could be an attractive building block for Bluetooth Low Energy (BLE) and other wireless technologies to support a wide range of Internet of Things (IoT) applications.

As a key building block of wireless communication systems, frequency synthesizers need to satisfy demanding requirements. Although analog PLL frequency synthesizers have been the standard for many years, engineers in the IoT industry are increasingly turning their attention to so-called digital PLLs (DPLLs) to achieve ultra-low power operation.

Kenichi Okada, associate professor at Tokyo Institute of Technology's Department of Electrical and Electronic Engineering and his group now report a fractional-N DPLL[2] that achieves a power consumption of only 265 microwatts (μW), a figure that is less than half the lowest power consumption achieved to date (980 μW). (Table 1)

The researchers found that overall power consumption could be greatly reduced by using an automatic feedback control system. "This automatic-switching feedback path consumes a power of 68 μW, which leads to a power consumption of 265 μW for the whole DPLL," Okada says.

The promising DPLL could go on to be used as a component for processors, memories and a vast new range of IoT devices that will be expected to be both cost-effective and eco-friendly by running on ultra-low power. Okada notes that early experiments show the DPLL could extend battery life by four times.

This paper is partially based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO).

This work is being presented in the Frequency Synthesizers session at the 2019 International Solid-State Circuits Conference (ISSCC), the world's leading annual forum on solid-state circuits and systems-on-a-chip.

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Technical terms

[1] Phase-locked loop (PLL): A control system used as a basic component of many radio, wireless and telecommunication technologies. The present study draws on the ability of PLLs to generate a stable frequency at multiples of an input frequency.

[2] Fractional-N DPLL: An emerging class of digital PLLs that are of much interest as they can help improve phase noise.

Related links

Tokyo Tech slashes power consumption in Bluetooth Low-Energy transceiver by more than half https://www.titech.ac.jp/english/news/2018/040426.html

Kenichi Okada - Wiring the world wirelessly https://www.titech.ac.jp/english/research/stories/faces8_okada.html

Okada Lab. http://www.ssc.pe.titech.ac.jp/english/research.html

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