News Release 

Designer-defect clamping of ferroelectric domain walls for more-stable nanoelectronics

Improved stability a significant step forward for domain-wall nanoelectronic data storage

ARC Centre of Excellence in Future Low-Energy Electronics Technologies

A UNSW study published today in Nature Communications presents an exciting step towards domain-wall nanoelectronics: a novel form of future electronics based on nano-scale conduction paths, and which could allow for extremely dense memory storage.

FLEET researchers at the UNSW School of Materials Science and Engineering have made an important step in solving the technology's primary long-standing challenge of information stability.

Domain walls are 'atomically sharp' topological defects separating regions of uniform polarisation in ferroelectric materials.

Domain walls in ferroelectrics possess fascinating properties, and are considered separate entities with properties that are dramatically different from the parent bulk ferroic material.

These properties are brought about by changes in structure, symmetry and chemistry confined within the wall.

"This is the fundamental starting point underpinning domain wall nanoelectronics," says study author Prof Jan Seidel.

The 'switching' property of ferroelectric materials makes them a popular candidate for low-voltage nanoelectronics. In a ferroelectric transistor, distinct polarisation states would represent the computational 0 and 1 states of binary systems.

However, the stability of that stored polarisation information has proven to be a challenge in application of the technology to data storage, especially for very small nanoscale domain sizes, which are desired for high storage densities.

"The polarisation state in ferroelectric materials decays typically within days to a few weeks, which would mean information storage failure in any domain-wall data storage system," says author Prof Nagy Valanoor.

The period of time that information can be stored in ferroelectric materials, ie the stability of the stored polarisation information, is thus a key performance feature.

To date, this long-standing issue of information instability has been one of the main limitations on the technology's application.

The study investigates the ferroelectric material BiFeO3 (BFO) with specially introduced designer defects in thin films. These designer defects can clamp down domain walls in the material, effectively preventing the ferroelectric domain relaxation process that drives information loss.

"We used a 'defect engineering' method to design and fabricate a special BFO thin film that is not susceptible to retention loss over time," says lead author Dr Daniel Sando.

VOLTAGE-DEPENDENT DOMAIN FORMATION

Pinning of domain walls is thus the main factor utilised to engineer very long polarisation retention.

"The novelty of this new research lies in precisely-controlled pinning of the domain wall, which allowed us to realise superior polarisation retention," says lead author Dawei Zhang.

The research provides critical new thinking and concepts for domain-wall based nanoelectronics for non-volatile data storage and logic device architectures.

In addition the mixed phase BFO-LAO system is a fertile ground for other intriguing physical properties, including piezoelectric response, field-induced strain, electrochromic effects, magnetic moments, electrical conductivity and mechanical properties.

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THE STUDY

The paper 'Superior polarization retention through engineered domain wall pinning' was published in Nature Communications today (DOI 10.1038/s41467-019-14250-7).

As well as funding from the Australian Research Council (Discovery, LIEF and Centre of Excellence programs), support was received by the Australian Government Research Training Program Scholarship (co-author Dawei Zhang). Invaluable equipment and technical support was provided by the Monash Centre for Electron Microscopy (MCEM). Thanks also go to Thomas Young and Vicki Zhong (UNSW) for assistance with sample preparation.

FERROELECTRIC MATERIAL STUDIES AT FLEET

Jan Seidel and Nagy Valanoor lead research teams within FLEET, the ARC Centre of Excellence in Future Low-Energy Electronics Technologies.

Jan Seidel's team perform key scanning probe microscopy (SPM) based research, with a particular focus on the utilisation of complex oxide materials systems. Seidel uses advanced SPM techniques to pattern electrical or magnetic order in topological materials at the nanoscale.

Nagy Valanoor's team explores oxides and thin-film materials as a platform for new, low-energy topological devices, and synthesises many of the ferroelectric and ferromagnetic heterostructures, and novel topological oxides, used by other FLEET researchers seeking low-energy transistors.

Ferroelectric materials are investigated within FLEET's Research theme 1, seeking to create a new generation of ultra-low energy electronics.

FLEET is an Australian Research Council-funded research centre bringing together over a hundred Australian and international experts to develop a new generation of ultra-low energy electronics.

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