Artistic rendering of an array of ferroelectric tunnel junctions for next-generation memory device (IMAGE)

Institute of Science Tokyo

Artistic rendering of an array of ferroelectric tunnel junctions for next-generation memory device

Caption

This image, featured on the outside front cover of the Nanoscale journal issue in which this paper was published, illustrates a conceptual arrangement of ferroelectric tunnel junctions in a next-generation memory architecture. The polarization state at each junction, depicted as with and without accumulation of positive charges, modulates electron tunneling between the top Ti/TiOx electrode and the underlying bottom platinum electrode, enabling distinct resistance states for memory operation.

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Copyright © 2026 Nanoscale Image link: https://doi.org/10.1039/d5nr04010h

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