Figure 2 (IMAGE)
Caption
(a) Photograph of test chips fabricated on a silicon substrate using semiconductor integrated circuit manufacturing processes. (b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater Technology, followed by fabrication of the spintronic devices at the Research Institute of Electrical Communication, Tohoku University. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations.
Credit
©Shunsuke Fukami, William A. Borders et al.
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