Figure 2. Die micrograph of the proposed transceiver (IMAGE)
Caption
The proposed phased-array transceiver is fabricated using a 65-nm CMOS process and packaged with wafer-level chip-scale package. It is configured in an area as small as 5 × 4.5 mm.
Credit
2021 Symposia on VLSI Technology and Circuits
Usage Restrictions
None
License
Licensed content