News Release

Memristor chip accelerates compressed sensing by 11 times through hardware-software co-optimization

A novel computing-in-memory (CIM) accelerator with memristor uses a co-optimization framework to overcome hardware non-idealities, achieving near-software accuracy for compressed sensing at the edge.

Peer-Reviewed Publication

Science China Press

As artificial intelligence (AI) and the Internet of Things (IoT) drive explosive data growth at the edge, compressed sensing (CS) is a key technique that reduces the hardware burden by sampling less data. However, reconstructing this compressed data on traditional CMOS hardware suffers from high energy consumption and latency caused by the "von Neumann bottleneck", which necessitates inefficient data shuttling between processor and memory.

To address this challenge, a research team from Tsinghua University, led by Associate Professor Jianshi Tang and Professor Huaqiang Wu, has developed a memristor-based compressed sensing accelerator (memCS). As reported in the journal National Science Review, the accelerator uses a 128Kb memristor chip with the computing-in-memory (CIM) architecture, to execute core calculations directly within the memory, eliminating the data movement bottleneck.

To mitigate the accumulation of computing errors caused by the inherent non-ideal characteristics of memristor chips during compressed sensing reconstruction iterations, the team developed a hardware-software co-optimization framework. This framework strategically integrates the mathematical constraints of compressed sensing with the characteristics of memristor hardware. The experimental results demonstrate the effectiveness of such framework. The optimized memCS, tested on the ImageNet dataset, achieves an average Peak Signal-to-Noise Ratio (PSNR) of 31.11 dB and a classification accuracy of 94.2%, both of which are nearly identical to software implementation.

In terms of system performance, the memCS accelerator is 11.22 times faster and 30.46 times more energy-efficient than a state-of-the-art GPU, highlighting its significant advantages for edge computing applications. This research opens a viable pathway for designing high-performance, energy-efficient compressed sensing systems for power-constrained edge scenarios.

The work was primarily conducted by the School of Integrated Circuits at Tsinghua University. Master's student Yunrui Jiao and Ph.D. student Han Zhao are the co-first authors. Associate Professor Jianshi Tang and Professor Huaqiang Wu are the corresponding authors. Collaborators include Professor He Qian and Professor Bin Gao of Tsinghua University, and Professor Biao Sun of Tianjin University.


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