News Release

A monolithic InP/SOI platform for integrated photonics

Peer-Reviewed Publication

Light Publishing Center, Changchun Institute of Optics, Fine Mechanics And Physics, CAS

Figure 1 | Monolithic InP/SOI platform with InP sub-micron wire and large dimension membrane arrays.

image: a, Cross-section schematic of selective lateral heteroepitaxy of InP. b, InP sub-micron wire array. c, Large dimension InP membrane array. d, In-plane InP grown from {111} Si facet. e, InP membrane on SOI. view more 

Credit: by Zhao Yan, Yu Han, Liying Lin, Ying Xue, Chao Ma, Wai Kit Ng, Kam Sing Wong, and Kei May Lau

Photonic integrated circuit (PIC) has been the backbone for low-power and high-speed datacom/telecom communication systems, and is the enabling technology for a variety of emerging applications, including high performance computing, automobile, quantum communication, optical sensing, etc. While Si photonics enjoys the economy of scale provided by the CMOS industry, the lack of an efficient and monolithically integrated light source has been an imperfection of this technology for decades. In recent years, monolithic integration of III-V light sources on mainstream Si platform via heteroepitaxy is widely regarded as the ultimate solution for fully integrated Si-photonics.


Practical application demands the III-V light sources grown on Si to satisfy three criteria: low defect density for reliable device operation, large dimension for fabrication of electrically driven lasers, and efficiently light coupling with Si-waveguides. While current approaches such as blanket deposition of III-V thin films on Si wafers or selectively growing III-V nano-structures on Si could meet one or two of the three criteria, they cannot fulfill all three requirements simultaneously and often improve one parameter at the expense of another.


In a new paper published in Light Science & Application, the research team led by Prof. Kei May Lau and postdoc researcher Yu Han from the Photonics Technology Center of the Hong Kong University of Science and Technology, doctoral student Zhao Yan and co-workers have developed a monolithic InP/SOI platform to simultaneously meet the three critical requirements. In their approach, both InP sub-micron wires and large dimension membranes are selectively grown on (001) SOI wafers using a novel growth method: lateral aspect ratio trapping. First, the defect necking effect of this approach results in dislocation-free InP on SOI. Second, large-area InP membrane is obtained via creating ultra-deep lateral oxide trenches and changing the growth direction from the prevailing vertical to lateral. Third, the epitaxial InP manifests an in-plane configuration and is positioned intimately with the Si device layer, which promotes efficient light interfacing.


In addition, the InP sub-micron wire array and large dimension InP membranes feature a unique InP-on-insulator (InPoI) characteristic and, similar to silicon-on-insulator, represent an ideal platform for implementing photonic functionalities. The authors exemplified the potential and versatility of this unique InP/SOI platform through the demonstration of optically-pumped lasers with different cavity designs, including subwavelength Fabry-Perot cavity, square cavities, and micro-disks.


Depending on the targeted device functions, the InP membranes can serve as templates for the regrowth of a variety of III-V structures for light emission, modulation and detection. For example, buried hetero-structure including InGaAs quantum wells and InAs quantum dots could be formed through selective vertical regrowth. The InP sub-micron wires, formed through the replacement of Si sub-micron fins, are ideal building blocks for subwavelength PICs and could also potentially enable the close integration with Si-based nano-electronics. In addition, the unique InPoI resembles InP directly bonded onto oxide layers, and accordingly the InP/SOI platform could benefit from the well-established processing technologies developed in the III-V heterogeneous integration approach.

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