image: Fig. 1. (a) Schematics of the SSA fabrication process. (b) SEM images of the SSA during the ICP etching process. (c–e) SEM images of the subulate RRAM devices with different c-radii. (f) 3D profile of uniform SSA from a typical region of the substrate. view more
Credit: ©Science China Press
This study is led by Ying Zhang (doctoral student, Institute of Microelectronics, Chinese Academy of Sciences) and Dr. Xiaolong Zhao (postdoctor, School of Microelectronics, University of Science and Technology of China). Si subulate array (SSA) substrates with different curvature radii fabricated by a low-cost, CMOS-compatible, nanoscale-controllable, and wafer-scale process were utilized to configure highly uniform RRAM devices. The fabrication process of the Ag/ZrO2/Pt subulate device was shown in Fig. 1. The SSA substrate was prepared via inductively coupled plasma (ICP) etching the planar Si substrate. The smallest curvature radius (c-radius) was achieved with a critical ICP etching time. The c-radius of the tip region (TR) can be further controlled by prolonging the etching time. Subsequently, Pt/ZrO2/Ag RRAM devices were prepared on the SSA substrates (one tip per cell).
Compared with the control device with a planar Si substrate, the RRAM devices with subulate substrates exhibit significantly improved cycle-to-cycle and device-to-device uniformity (Fig. 2 and 3). Decreasing the c-radius significantly improves the device performance, including the resistive window, retention characteristics, and uniformity of switching voltages (VSET and VRESET) and resistance.
To determine the effects of the SSA strategy on conductive filament (CF) formation, the Pt/ZrO2/Ag subulate device after the SET process was investigated by transmission electron microscopy and energy dispersive spectroscopy characterization. CFs were demonstrated to be generated in the TR of the subulate device, where the electric field is enhanced by the tip with a small c-radius.
The SSA substrates enhance the local electric field, control a few CFs formed in the TR of each device, and further optimize the device switching performance. The low-cost SSA fabrication process is fully compatible with standard CMOS process for largescale integration. The proposed SSA provides a low-cost, uniform, CMOS-compatible, and nanoscale-controllable optimization strategy for the large-scale integration of highly uniform RRAM devices.
See the article:
CMOS-compatible wafer-scale Si subulate array for superb switching uniformity of RRAM with localized nanofilaments
https://doi.org/10.1007/s40843-021-1956-9
Journal
Science China Materials