The Center for Advanced Electronics through Machine Learning (CAEML), which has been funded as a Phase I IUCRC by the National Science Foundation since 2017, has just received funding from NSF to proceed with a second five-year phase. Phase II research will officially kick off on August 1, 2022.
CAEML’s research vision is to apply machine learning to the design of optimized microelectronic circuits and systems, thereby increasing the efficiency of electronic design automation (EDA) and resulting in reduced design cycle time and radically improved reliability.
In keeping with the nature of NSF’s IUCRC (Industry–University Cooperative Research Center) program, CAEML is centered around partnerships with industry members who contribute research funding and help guide the center’s research by identifying the greatest industry needs and serving as mentors for research projects. Administrative costs are covered by NSF, and industry participants get rights to IP and access to top-notch graduate students who perform industry-relevant research.
According to CAEML director Elyse Rosenbaum, “The university participants are gratified by the knowledge that their work will affect industry practice. Center participation is especially beneficial for the students and the junior faculty, who learn about real-world technical challenges and get to apply their creativity and knowledge to the solutions.”
Phase I accomplishments to date include publication of over 70 papers (some with industry co-authors), delivery of 20 webinars, and receipt of 11 awards or award nominations. Twelve students who participated in CAEML’s Phase I have already been hired into full-time positions by CAEML member companies. In addition, prior to graduation, many students have held summer internships at CAEML companies.
In Phase II, the CAEML team will focus its attention on five technical challenges identified by the center’s industry advisory board: analog circuit design in advanced semiconductor technologies; end-to-end channel models for signal integrity analysis; security of design IP, signals, and data; system models that provide actionable insight to sustain system reliability; and secure access to proprietary data for machine learning (ML), to facilitate research cooperation among companies and between companies and universities.
Rosenbaum says, “Leveraging research results from Phase I, the Phase II CAEML is expected to make significant advances in design optimization and efficiency by developing the capability to learn inverse surrogate models, e.g., an inverse neural network, that provide a mapping from the design specifications to suitable design realizations. The center will continue its work on interconnections of component-level ML models, recognizing that the accuracy of the end-to-end system model is of the utmost importance. CAEML will continue to demonstrate models that account for variability and uncertainty, which is a requirement to achieve a high manufacturing yield.”
CAEML is a partnership among the University of Illinois Urbana-Champaign, North Carolina State University, and the Georgia Institute of Technology. In addition to director Rosenbaum, who is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at UIUC, the leadership team consists of Paul Franzon, who is the Cirrus Logic Distinguished Professor of Electrical and Computer Engineering and Director of Graduate Programs in ECE at NCSU, and Madhavan Swaminathan, who is the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of the Packaging Research Center at Georgia Tech.
The center’s Phase I industry members have diverse interests in microelectronic circuits and systems. The center will welcome both old and new members to Phase II.