Scalable transition metal dichalcogenide memtransistor arrays for energy-efficient artificial neural networks

Researchers at the National University of Singapore (NUS) have fabricated ultra-thin memtransistor arrays from two-dimensional (2D) transition metal dichalcogenide (TMDC) with controllable Schottky barriers. These arrays are highly uniform, demonstrating low device-to-device variation and provide high performance for image recognition tasks.

Memtransistors are electronic devices that integrate data storage and signal processing within a single unit, making them attractive for compact, energy-efficient neuromorphic computing. However, practical artificial neural networks (ANNs) require large arrays of these devices, and achieving a high resistive switching ratio, consistent behaviour across devices, and scalability remains challenging. In 2D TMDC materials, atomic imperfections in the crystal tend to form randomly, affecting the device uniformity and scalability. Additionally, the non-uniform vacancy migration behaviour further exacerbates significant device-to-device variability and results in poor fabrication yield. These effects obscure the underlying switching mechanisms and introduce large performance variability across the array.

A research team led by Professor CHEN Wei from the NUS Department of Physics and the Department of Chemistry, fabricated ultra-thin molybdenum disulfide (MoS₂) memtransistor arrays with a 500 nm channel length and demonstrated precise Schottky barrier modulation. By carefully exposing selected areas to oxygen, they created and controlled a small number of sulfur vacancies, which allow them to fine‑tune the contact barriers so that electricity flows through the devices in a precise, predictable way. This research work was carried out in collaboration with Dr JIN Tengyu from Shanghai University, China.

The research findings were published in the scientific journal Nature Communications on 28 October 2025.

The fabricated memtransistors switch very clearly between the “on” and “off” states, changing the electrical current by about 10,000 times, and up to 100,000 times with gate modulation. The array is also extremely small with each device having a 500 nm long channel length and a cell size as small as 4.65 F². The devices performed consistently across the array, with less than 6.8 per cent variation from one device to another, and the fabrication yield can reach 100 per cent, indicating high uniformity and reliability. When these chips are used to build an artificial neural network for image recognition tasks, it achieves over 98 per cent accuracy in recognising and classifying pictures.

One of the authors, Dr HOU Xiangyu said, “This memtransistor fabrication approach is also applicable to mechanically exfoliated molybdenum disulfide and molybdenum ditelluride, indicating a versatile fabrication strategy for building 2D TMDC memtransistors.”

“Looking forward, integrating this approach with advanced fabrication techniques, multi-layer stacking, or hybrid CMOS-2D architectures could further enhance device performance and enable large-scale, energy-efficient AI accelerators,” added Prof CHEN.