Curvilinear mask technology for integrated circuit lithography

Lithography is the core technique for transferring circuit patterns onto wafers. As technology nodes shrink, traditional lithography hits severe physical diffraction limits. It also faces equipment bottlenecks and random process variations. Traditional chip layouts use strict horizontal and vertical lines, known as orthogonal or Manhattan structures. However, 90-degree corners are highly sensitive to manufacturing fluctuations. They easily amplify mask errors and lead to manufacturing failures.

 

Curvilinear mask technology has emerged to solve this problem. It originates from inverse lithography technology (ILT). This method treats mask design as a mathematical inverse optimization problem. By solving this problem, it generates free-form, curved shapes that naturally follow optical physical laws.

 

These curved shapes offer massive advantages in both manufacturing and design. On the manufacturing side, curvilinear masks eliminate unstable sharp corners. This spreads errors evenly and significantly widens the manufacturing process window. On the design side, curved routing breaks the limits of orthogonal space. Bottom-layer metals can connect nodes using the shortest possible paths. This not only compresses the cell area but also reduces the need for upper metal layers and vias. Consequently, it lowers wafer costs and boosts overall circuit performance.

 

To achieve mass production, researchers have advanced five key technological areas.

First, layout design has evolved. Increasing transistor density causes severe internal routing congestion. Researchers introduced non-orthogonal curved interconnects to bypass physical obstacles. This achieves the shortest distance connections and efficiently utilizes bottom-layer metals.

 

Second, optical proximity correction (OPC) has been upgraded. Generating curvilinear masks requires massive computational power. The industry tackles this using hardware acceleration and artificial intelligence. Deep learning networks embedded with physical models now replace slow traditional iterations. Meanwhile, parametric curve representation balances image fidelity with data volume.

 

Third, mask rule checks (MRC) and process corrections have been reconfigured. Approximating curves with polygons causes precision loss and data redundancy. Researchers proposed a "rolling circle" check theory based on the minimum manufacturable circle. Native curve algorithms now directly evaluate mathematical curves, drastically improving speed and accuracy.

 

Fourth, mask writing technology has broken previous capacity bottlenecks. Traditional variable-shaped beam (VSB) writers struggle with complex curves due to explosive shot counts. Multi-beam mask writers (MBMW) solve this issue. They use thousands of micro-beams for pixelated scanning, making writing time entirely independent of pattern complexity.

 

Finally, wafer metrology has shifted from one-dimensional to two-dimensional paradigms. Traditional linear measurements fail on curved shapes. By extracting actual 2D edges from scanning electron microscope images, researchers have established new statistical error evaluation standards.

 

Moving to full-scale mass production still faces hurdles. Full-chip optimization demands immense computing power, and polygon-based data formats cause severe data explosions. To overcome this, the industry is upgrading data standards to natively support parametric curves. The future points toward a highly integrated "Design-Mask-Wafer" co-optimization framework. AI-driven metrology will provide continuous feedback to earlier design stages, creating a closed-loop system to systematically eliminate manufacturing defects.

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